MIOS V1.7 hardware mods

This page summarizes all hardware modifications which are required from MIOS V1.7 and higher. The reasons for these changes are described in this forum article.

separate DIN/DOUT Shift Register clock

With MIOS V1.7, the shift register clock of the DIN/DOUT chain must be a dedicated output, no other module or peripheral should be driven from the same pin (#22/RD3), otherwise you will notice flickering LEDs or not-working buttons/encoders.
This means no change on the wiring to J8/J9, this means only that J10:SC shouldn't be used by any other module anymore.

BankStick connection to the Core

The IIC clock line J4:SC (BankStick) is now connected to pin (#28/RD5) of the core module. Thats an easy change, since it's normaly an isolated cable. Take a look into the MBHP_CORE schematic or the MBHP_CORE PCB quick view to locate the correct pin.

SID module connection to the Core

The SCLK line of the SID module has also to be connected to pin (#28/RD5) of the core module. Desolder the cable from junction CORE:J10:SC and solder it to CORE:J10:MD. See also mbhp_sid_c64_psu.pdf, mbhp_4xsid_c64_psu.pdf and mbhp_4xsid_c64_psu_optimized.pdf.

Last update: 2024-05-08