Differences between MBHP_SID_V3 and MBHP_SID_V2

This page contains some old docs which are only required if you are going to populate the an old version of the SID module. The most current version is documented here.
The main differences:

• the 1 MHz oscillator has been removed from the circuit. If the SID clock runs asynchronous to the PIC, it can happen that the gate of an DCO will be triggered unintentionally. The details are described in this forum article
  Now it's strongly recommended to clock the SID module from Core::J7:SO/PIC Pin #17 instead
• The wiring to J2 has been rearranged, so that a 1:1 connection to J10 of the Core module is possible again
• R1 (a 10k pull-up) has been removed, because it was only an artefact from my first experiments and not really required
• two bypass caps C13 and C14 have been added to improve the power integrity.

Download

PCB data, can be viewed, modified and converted with Eagle Light. The .pdf based schematic has been created with xcircuit. There are no special eagle schematics available, since components have been netlisted in the .brd file directly!
Module	Schematic	Layout Data	Quick-view
MBHP_SID_V2	mbhp_sid_v2.pdf	mbhp_sid_v2.brd	mbhp_sid_v2.gif

MBHP_CORE -> MBHP_SID_V2 interconnections

This diagram shows, how a V2 module has to be connected to the core:

Soldering Guide

	Start with soldering the 5 bridges which save you from creating a 2-layer board. You can use the cutted legs of caps and resistors, before you throw them away after you finished all the modules! :-)
	Add also the two additional Bypass Caps between Vdd and ground (Vss) of each 74HC595 on the bottom side of the PCB as close to the +5V power input of the 74HC595 as possible. They improve the power integrity.
	Mount all the parts with the exception of the three ICs. Apply power to the module and check the voltage level between pin IC1:Vdd(28) and IC1:Vss(14) - it must be 12V for the 6581 SID, 9V for the 8580 SID.
	Now connect port J2 of the SID module with port J10 of the core module like described above - no 1:1 connection! Ensure the following voltage levels: IC1:Vcc(25) - IC1:Vss(14) = 5V IC2:Vdd(16) - IC2:Vss(8) = 5V IC3:Vdd(16) - IC3:Vss(8) = 5V
	As descriped above, the clock must be supplied from Core::J7:SO (PIC Pin #17, which is configured as 1MHz PWM output with 1:1 duty cycle) - this requires an additional cross connection between MBHP_SID and MBHP_CORE.

Testing

Most of the details are described in the MIDIbox SID Walkthrough. Here a summary in short words: once you've uploaded the MIDIbox SID application, you can play some notes over MIDI channel #1.
If you don't hear a sound, upload the sid_testtone application in order to ensure that the core can access the SID module. If you still don't hear a sound, try the mbsid_interconnection_test in order to check if all interconnections between CORE and SID module are working.
These three programs can be downloaded from the MIOS Download page.

Copyright © 1998-2023, Thorsten Klose. All rights reserved.